1. Field of the Invention
The present invention lies in the field of semiconductor memory devices and, more specifically, pertains to improved methods and apparatus for built-in self test of such devices.
2. Description of the Prior Art
As semiconductor memory manufacturing techniques advance and ever greater density is achieved, it is now common to see complete memory systems contained in a single integrated circuit chip. As DRAM densities increase, testing such circuits is increasingly challenging due to the large number of memory cells and multiple memory blocks within a single chip. Testing time is critically important, and testing techniques are limited by available chip area and pin limitations.
Generally, two methods for testing a packaged RAM are distinguished by the place where a test pattern is generated. One method uses external test equipment and the other is by a built-in self test (BIST) circuit, i.e. on-board the memory IC. The test method using external test equipment has an advantage in that it is easy to test the RAMs by using various patterns. The test equipment can be programmed as desired. However, in order for the test equipment to interface to an address data input, a data output and control signals of each block of RAM during a test mode of operations, all ports of the RAMs must be connected to a pin which is accessible by the test equipment, and accordingly overhead is incurred in routing and the use of the pins. Alternatively, the pins can be multiplexed with respect to the RAM blocks, but since the RAM blocks then cannot be simultaneously tested, the test time increases.
In the test method using the BIST circuit, if a BIST mode is set from the exterior, the BIST circuit is activated and the RAMs are tested by applying a predetermined test pattern. The test result indicates whether or not an error was produced. Since the number of external connections needed for such testing is minimized, the RAM blocks can be simultaneously tested and therefore test time is reduced. However, since a test circuit for generating the test pattern is added on-board the IC, chip area overhead is incurred and the test pattern is fixed. What is needed, therefore, is improved self-test methods and apparatus for providing rapid functional testing of multiple blocks of RAM while minimizing chip area and pin count.